Electromigration (EM) is a phenomenon causing material transport in a conductor through a gradual movement or drift of ions, for example, due to momentum transfer between electrons in the conductor and diffusing metal atoms in an interconnect. In the semiconductor field, this electromigration phenomenon often appears in integrated circuits when high current densities are present on a conductive structure. The gradual movement of ions in these integrated circuits can cause electrical problems, such as integrated circuit failure due to open circuits and/or short circuits.
Semiconductor manufacturers or foundries can identify design rules based on the electromigration phenomenon, which can provide limitations on wires or other conductive structures in the integrated circuits based on current densities associated with those structures. These design rules may be specified in a variety of different file formats, such as Interconnect Technology Format (ITF), Unified Interconnect Modeling Format (iRCX), Portable Document Format (PDF) documents, or the like, each of which can express electromigration design rules for limit computation specific to the semiconductor manufacturer.
Designers of integrated circuits can utilize one or more design rule checking tools to analyze a layout design of an integrated circuit for violations of the electromigration design rules. The layout design may describe the integrated circuit in a GDSII file format, an Open Artwork System Interchange Standard (OASIS) format, Library Exchange Format (LEF), Design Exchange Format (DEF), or the like. The design rule checking tools can parse the electromigration design rules from the design rule files generated by the semiconductor manufacturer and generate in-memory models of the electromigration design rules, for example, generating condition trees and/or expression trees for the electromigration design rules, which the design rule checking tools load into memory for utilization during the design rule check operations.
During an electromigration check, the design rule checking tools can execute an electromigration check program to identify portions of the layout design for the integrated circuit having conductive structures and to evaluate the identified portions of the layout design against the electromigration design rules. Specifically, the design rule checking tools implementing the electromigration check program traverse the condition trees and/or expression trees to generate input data to the electromigration check program for use in the evaluation of whether physical configuration and/or electrical characteristics of the conductive structures conform to the electromigration design rules. While this technique can identify whether the layout design conforms to the electromigration design rules, the generation of in-memory condition trees and/or expression trees consumes memory resources, and the utilization of the in-memory condition trees and/or expression trees to generate input to the electromigration check program slows evaluation of the layout design for conformance to the electromigration design rules by the design rule checking tools.